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	A Microwatt/Channel Neural Signal Processor for High-Channel-Count Spike Detection and Sorting 会议论文 2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), Singapore, Singapore, 19-22 May 2024 作者: Zichen Hu; Zhining Zhou; Hongming Lyu Adobe PDF(1901Kb) \| 收藏 \| 浏览/下载：284/4 \| 提交时间：2024/07/08 Brain computer interface Clustering algorithms Computer circuits Logic devices Brain-computer interface Features extraction High channel counts Low Power Microwatts Neural signal processing Neural signals Second derivatives Spike detection Spike-sorting
	A 12-bit 75 MS/s Asynchronous SAR ADC with Gain-Boosting Dynamic Comparator 会议论文 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), Singapore, Singapore, 19-22 May 2024 作者: Chen, Renhe; Lee. Albert; Hu, Yongqi; Xu, Hao; Kou, Xufeng Adobe PDF(1115Kb) \| 收藏 \| 浏览/下载：483/2 \| 提交时间：2023/11/22 Analog to digital conversion Approximation theory Comparator circuits Computer circuits Digital to analog conversion Energy efficiency Feedback Frequency converters Signal to noise ratio Analog to digital converters Asynchronous logic Dynamic comparators Gain boosting High gain Integration phase Low delay Pre-amplifiers Successive approximation register Successive approximation register analog-to-digital converter
	JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits 会议论文 2024 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), Valencia, Spain, 25-27 March 2024 作者: Siyan Chen; Rongliang Fu; Junying Huang; Zhimin Zhang; Xiaochun Ye Adobe PDF(654Kb) \| 收藏 \| 浏览/下载：223/0 \| 提交时间：2024/06/17 Alignment Computation theory Computer circuits Computing power Dynamic programming Heuristic methods Timing circuits Computing technology Length matching Low-power consumption Placement Rapid single flux quantum circuits Rapid single-flux quantum logic Rapid single-flux-quantum Superconducting logic Timing alignment Wire length
	RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: PP, 期号: 99, 页码: 1-1 作者: Rui Li; Lin Li; Heng Yu; Masahiro Fujita; Weixiong Jiang Adobe PDF(6854Kb) \| 收藏 \| 浏览/下载：328/10 \| 提交时间：2024/08/26 Benchmarking Boolean functions Constraint satisfaction problems Integer programming Multiplying circuits Program debugging Reverse engineering Software design Trees (mathematics) Binary decision Binary decision diagram Computer algebra Decision diagram Logic Logic-optimized multiplier Optimisations Satisfiability Symbolic computer algebra
	Modeling and Optimization of XOR Gate Based on Stochastic Thermodynamics 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, 2024, 卷号: 71, 期号: 1, 页码: 348-358 作者: Peng, Xiaoxuan; Ge, Xiaohu; Ha, Yajun Adobe PDF(1654Kb) \| 收藏 \| 浏览/下载：300/1 \| 提交时间：2024/04/12 Circuit simulation CMOS integrated circuits Computer circuits Digital communication systems Digital integrated circuits Energy utilization Field effect transistors Logic circuits Logic gates MOS devices Optimization Oxide semiconductors Signal encoding Single electron transistors Stochastic models Stochastic systems Thermodynamics Timing circuits Energy consumption model Energy consumption optimization Energy-consumption Integrated circuit modeling Parity check Parity check circuit Parity check codes Single-electron transistors Stochastic thermodynamics XOR gates
	Timing verification of rapid single flux quantum logic cell 期刊论文 PHYSICA C: SUPERCONDUCTIVITY AND ITS APPLICATIONS, 2023, 卷号: 610 作者: Weng, Bicong; Gao, Xiaoping; Ren, Jie; Li, Xiuting; Niu, Minghui Adobe PDF(5709Kb) \| 收藏 \| 浏览/下载：297/0 \| 提交时间：2023/06/09 Cells Computer circuits Cytology Delay circuits Integrated circuit manufacture Josephson junction devices Oscillators (electronic) Quantum optics Reliability analysis Hold time Hold time test Process corner Set-up time Setup time test Single flux quantum logic Superconducting electronics Timing parameters Timing verification Verification method
	JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits 会议论文 PROCEEDINGS OF THE ACM GREAT LAKES SYMPOSIUM ON VLSI, GLSVLSI, Knoxville, TN, United states, June 5, 2023 - June 7, 2023 作者: Chen, Xinda; Fu, Rongliang; Huang, Junying; Cao, Huawei; Zhang, Zhimin Adobe PDF(1863Kb) \| 收藏 \| 浏览/下载：343/0 \| 提交时间：2023/07/14 Computation theory Computer circuits Energy efficiency Timing circuits Length matching Manhattan routing Multi terminals Rapid single flux quantum circuits Rapid single-flux quantum logic Rapid single-flux-quantum Routing model Routings Rsfq Superconducting logic
	Data acquisition of bunch IDs in timing system of SHINE beamlines and end stations 期刊论文 HE JISHU/NUCLEAR TECHNIQUES, 2023, 卷号: 46, 期号: 6 作者: Yin, Liang; Zeng, Mengqi; Yin, Congcong; Huai, Ping Adobe PDF(1211Kb) \| 收藏 \| 浏览/下载：200/0 \| 提交时间：2024/04/12 Cameras Data handling Electrons Free electron lasers Programmable logic controllers Software testing System-on-chip Timing circuits X ray detectors Beam-lines Bunch ID End stations High repetition rate SHINE Testing systems Timing Timing systems White rabbit protocol X-ray free electron lasers
	A 4/5 or 8/9 High-Speed Wide Band Programmable Prescaler 会议论文 2023 3RD ASIA-PACIFIC CONFERENCE ON COMMUNICATIONS TECHNOLOGY AND COMPUTER SCIENCE (ACCTCS), null,Shenyang,PEOPLES R CHINA, FEB 25-27, 2023 作者: Li, Jinjian; Tian, Tong Adobe PDF(500Kb) \| 收藏 \| 浏览/下载：361/1 \| 提交时间：2023/05/07 Divider-by-4/5 and 8/9 dual modulus prescaler TSPC Asynchronous prescaler CMOS integrated circuits Computer circuits Frequency dividing circuits Logic gates Asynchronoi prescaler Dual-modulus prescalers Gate levels High Speed Maximum operating frequency Prescalers Speed optimization Wide-band
	A Recursion and Lock Free GPU-based Logic Rewriting Framework Exploiting Both Intra-node and Inter-node Parallelism 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: PP, 期号: 99, 页码: 1-1 作者: Li, Lin; Li, Rui; Ha, Yajun Adobe PDF(7297Kb) \| 收藏 \| 浏览/下载：454/2 \| 提交时间：2023/03/17 Boolean functions Computer circuits Computer graphics Concurrency control Data structures Locks (fasteners) Logic Synthesis Program processors AIG rewriting GPU accelerations Instruction set Lock-free Logic rewriting Parallel processing Recursions Rewriting algorithm Schedule Time consuming techniques

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