上海科技大学知识管理系统

To reduce the energy consumption of digital communication systems, chips based on the complementary metal-oxide-semiconductor (CMOS) technology are facing the challenge of low energy consumption for signal processing in communication systems. Some typical technologies, such as shortening the transistor size, reducing the number of electrons and lowering the supply voltage are widely used by present chips to achieve low energy consumption. However, as the gate size of transistors is getting closer to the mesoscopic scale, how to model and analyze the non-equilibrium information processing of transistors is an essential challenge for digital integrated circuits. In this paper, based on the stochastic thermodynamics theory, an energy consumption model of a single electron transistor XOR gate considering the input state transition is proposed. Moreover, the Landauer limit and mismatch theory are combined to derive the lower bound of the energy consumption of XOR gate for one operation. Simulation results show that the average energy consumption of XOR gate is the lowest when the supply voltage is five times the thermal noise voltage. Based on the proposed energy consumption model of XOR gate, an energy consumption model of parity check circuits is proposed. Then an optimization algorithm is designed to reduce the energy consumption of parity check circuits. Compared with the energy consumption of parity check circuits without optimization, simulation results show that the energy consumption of parity check circuits using the energy consumption optimization algorithm is maximumly reduced by 41.71%. © 2004-2012 IEEE.