上海科技大学知识管理系统

This paper presents a 10-bit 3.84-MS/s ping-pong interleaving successive approximation register (SAR) ADC designed for a 96-channel neural signal acquisition system. The ADC incorporates an input buffer and peripheral circuits which allow it to directly connect the front-end array. A ping-pong interleaving structure is adopted to double the sampling rate at a given SPI clock frequency while minimizing the power consumption of the input buffer. Unlike conventional time-interleaved ADCs, the proposed technology does not suffer from any mismatches among sub-ADCs. The ADC is fabricated in a 0.18-μm CMOS technology. It achieves an effective-number-of-bit (ENOB) of 9.45-bits at a 3.84-MS/s sampling rate with a perchannel power consumption of 17.5 μW. This work achieves the highest figure-of-merit (FOM) among literatures on multi-channel signal acquisition systems.