上海科技大学知识管理系统

This paper proposes a successive-approximationregister (SAR) analog-to-digital converter (ADC) features a gainboosting dynamic comparator design and a low-delay SAR logic. The proposed comparator incorporates a positive feedback in the pre-amplifier, which enables a high gain during the integration
phase, thereby improving the energy efficiency. Meanwhile, to ensure a sufficient settling time for the internal capacitive digitalto-analog converter (CDAC), an asynchronous SAR logic with a low logic delay in the SAR logic loop is implemented. Accordingly, a prototype ADC is manufactured using the 28-nm CMOS technology, which achieves a power consumption of 860 𝜇W at 75 MHz sampling frequency. Moreover, the measured signal-tonoise and distortion ratio (SNDR) of the prototype at Nyquist frequency is 60.9 dB, which translates to a Walden figure of merit (FoMW) of 12.7 fJ/conversion-step.