Reliability- and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation

doi:10.1016/j.vlsi.2018.04.012

	Reliability- and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation
	Gao, Wei1,3,4 ; Qian, Zhiliang 2; Zhou, Pingqiang3
	2019-03
发表期刊	INTEGRATION-THE VLSI JOURNAL (IF:2.2[JCR-2023],1.6[5-Year])
ISSN	0167-9260
卷号	65 页码:351-361
发表状态	已发表
DOI	10.1016/j.vlsi.2018.04.012
摘要	Network-on-Chip (NoC)-based communication architecture is promising in addressing the communication bottlenecks in current and future multicore processors. In this work, we consider the application-specific mapping problem and electromigration (EM)-induced through-silicon via (TSV) reliability issue in tile-based three-dimension (3D) NoC architectures. In 3D NoCs, network contention may result in unacceptable communication delay among the processing cores and thus has significant effect on the system performance. So we propose a new latency model for the routers which characterizes the network contentions among different traffic flows from sharing of network resources. Then we solve the core mapping problem by a fast while efficient stochastic algorithm called Simulated Allocation (SAL), which integrates our new latency model and also aims to optimize the communication power, latency in the mapping procedure. After that, we use an incremental method to optimize the reliability of the TSVs. Experimental results show that, contention-aware model (CAM) has 25% larger network latency than our latency model; compared with particle swarm optimization (PSO), our SAL algorithm can achieve 7% less power with about 7.5 x run-time speedup; as for reliability, our method can achieve better results (up to 10 x increase in terms of the void nucleation time (VNT)) with 7.64% increased latency.
收录类别	SCI ; SCIE ; EI
语种	英语
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:000474316700032
出版者	ELSEVIER SCIENCE BV
WOS关键词	AWARE ; ENERGY ; OPTIMIZATION ; FLOW
原始文献类型	Article
引用统计	正在获取...
文献类型	期刊论文
条目标识符	https://kms.shanghaitech.edu.cn/handle/2MSLDSTB/29576
专题	信息科学与技术学院_博士生信息科学与技术学院_PI研究组_周平强组
通讯作者	Zhou, Pingqiang
作者单位	1.Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, Shanghai 200050, Peoples R China 2.Shanghai Jiao Tong Univ, Shanghai, Peoples R China 3.ShanghaiTech Univ, Sch Informat Sci & Technol, Shanghai 201210, Peoples R China 4.Univ Chinese Acad Sci, Beijing, Peoples R China
第一作者单位	信息科学与技术学院
通讯作者单位	信息科学与技术学院
推荐引用方式 GB/T 7714	Gao, Wei,Qian, Zhiliang,Zhou, Pingqiang. Reliability- and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation[J]. INTEGRATION-THE VLSI JOURNAL,2019,65:351-361.
APA	Gao, Wei,Qian, Zhiliang,&Zhou, Pingqiang.(2019).Reliability- and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation.INTEGRATION-THE VLSI JOURNAL,65,351-361.
MLA	Gao, Wei,et al."Reliability- and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation".INTEGRATION-THE VLSI JOURNAL 65(2019):351-361.