Subsystem under 3D-Storage Class Memory on a chip
Guo, Jipeng1,2; Wang, Haibo1,2; Jing, Weiliang3; Li, Haixin1,2,4; Du, Yuan1,2; Song, Zhitang1; Chen, Bomy1,3
AbstractIn this paper, we propose a subsystem architecture under 3D-Storage Class Memory (3D-SCM), termed SuS, to solve the memory and power wall problems. Placing the processing unit under the 3D-SCM achieves high performance. We evaluate SuS using gem5 and the GPGPU-Sim simulator. The simulation results for the central processing unit (CPU)-based SuS architecture reveal a 100% performance improvement and a 73% energy reduction compared to the CPU architecture using dual in-line memory modules and a 4% performance improvement with a 27% energy reduction compared to the CPU architecture using hybrid memory cube. Moreover, the graphics processing unit (GPU)-based SuS architecture simulation results on the neural network benchmark demonstrate performance improvements of 17% and 7% compared to GPU architectures with graphics double data rate series memory and high bandwidth memory, respectively. (C) 2019 Elsevier Ltd. All rights reserved.
Keyword3D-Xpoint phase change memory Subsystem under 3D-SCM nvSAN DaysRAM Artificial intelligence Near-data processing
Indexed ByEI ; SCI
Funding ProjectScience and Technology Council of Shanghai[17DZ2291300]
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Hardware & Architecture ; Computer Science, Interdisciplinary Applications ; Engineering, Electrical & Electronic
WOS IDWOS:000474672200004
EI Accession Number20190406402067
EI KeywordsArtificial intelligence ; Benchmarking ; Computer graphics ; Computer graphics equipment ; Data handling ; Memory architecture ; Network architecture ; Phase change memory ; Program processors
EI Classification NumberComputer Systems and Equipment:722 ; Computer Software, Data Handling and Applications:723
Original Document TypeArticle
Citation statistics
Cited Times [WOS]:0   [WOS Record]     [Related Records in WOS]
Document Type期刊论文
Corresponding AuthorGuo, Jipeng; Jing, Weiliang
Affiliation1.Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, State Key Lab Funct Mat Informat, Shanghai 200050, Peoples R China
2.Univ Chinese Acad Sci, Beijing 100049, Peoples R China
3.Shanghai Xinchu Integrated Circuit Inc, Shanghai 200122, Peoples R China
4.ShanghaiTech Univ, Sch Informat Sci & Technol, Shanghai 201210, Peoples R China
Recommended Citation
GB/T 7714
Guo, Jipeng,Wang, Haibo,Jing, Weiliang,et al. Subsystem under 3D-Storage Class Memory on a chip[J]. COMPUTERS & ELECTRICAL ENGINEERING,2019,74:47-58.
APA Guo, Jipeng.,Wang, Haibo.,Jing, Weiliang.,Li, Haixin.,Du, Yuan.,...&Chen, Bomy.(2019).Subsystem under 3D-Storage Class Memory on a chip.COMPUTERS & ELECTRICAL ENGINEERING,74,47-58.
MLA Guo, Jipeng,et al."Subsystem under 3D-Storage Class Memory on a chip".COMPUTERS & ELECTRICAL ENGINEERING 74(2019):47-58.
Files in This Item:
File Name/Size DocType Version Access License
10.1016@j.compelecen(2175KB)期刊论文未知限制开放UnknownView Application Full Text
Related Services
Usage statistics
Scholar Google
Similar articles in Scholar Google
[Guo, Jipeng]'s Articles
[Wang, Haibo]'s Articles
[Jing, Weiliang]'s Articles
Baidu academic
Similar articles in Baidu academic
[Guo, Jipeng]'s Articles
[Wang, Haibo]'s Articles
[Jing, Weiliang]'s Articles
Bing Scholar
Similar articles in Bing Scholar
[Guo, Jipeng]'s Articles
[Wang, Haibo]'s Articles
[Jing, Weiliang]'s Articles
Terms of Use
No data!
Social Bookmark/Share
File name: 10.1016@j.compeleceng.2019.01.009.pdf
Format: Adobe PDF
All comments (0)
No comment.

Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.