上海科技大学知识管理系统

本发明的一个技术方案是提供了一种面向可伸缩多晶粒片上网络FPGA架构的布局方法。本发明的另一个技术方案是提供了一种前述的面向可伸缩多晶粒片上网络FPGA架构的布局方法的应用。本发明公开了一个基于片上网络的可伸缩多晶粒FPGA架构与相应的层次化递归布局算法，旨在直接将由现有高层次综合生成的寄存器传输级数据流设计直接映射到所提出的互联架构上。本发明公开的方法能够发掘出层次化拓扑的潜力并更有效地利用专用互联资源，例如跨晶粒线网、片上网络与高速收发器。

One technical solution of the present invention provides a layout method for a scalable multi-die network-on-chip FPGA architecture. The other technical solution of the present invention provides an application of the layout method for a scalable multi-die network-on-chip FPGA architecture. The present invention provides a scalable multi-die FPGA architecture based on a network-on-chip and a corresponding hierarchical recursive layout algorithm, and aims to directly map a register-transfer level dataflow design generated by means of existing high-level synthesis to the proposed interconnection architecture. According to the method provided by the present invention, the potential of a hierarchical topology can be explored, and special interconnection resources, such as a cross-grain line network, a network-on-chip and a high-speed transceiver, can be utilized more effectively.