上海科技大学知识管理系统

Emerging applications are calling for significantly larger FPGAs with multi-dies. However, the interconnection architecture of existing FPGAs lacks scalability. The execution time and failure probability of their RTL-to-Silicon process increase dramatically with the growth of design and the number of dies. To address this issue, we propose both an NoC-based scalable multi-die FPGA architecture and a corresponding floorplanning framework, namely Hierarchical and Recursive Floorplanning Framework (HRFF). First, from the architecture side, we introduce an interconnection architecture with a class of scalable hierarchical topology. Second, for the algorithm side, we formulate the generic floorplanning problem for NoC-based architectures as a multi-objective Mixed Integer Linear Programming (MILP) problem, balancing the design timing and interconnection workload. Third, we develop a novel recursive approximate method to efficiently solve the multi-objective MILP formulation over the proposed architecture, with a configurable trade-off between solution quality and solver run time. Experimental results show that the scalability of our proposed technique is at least 1.5x on all and 3x on certain benchmarks as that of the state-of-the-art solutions with no loss of design throughput.