上海科技大学知识管理系统

Recent works show that multi-bit multiplications can be achieved in multi-cycles via serial in/near memory computing, aiming at reducing data transfers hence improving energy efficiency. However, the pure serial approach suffers from a long latency and leaves additional room to optimize energy efficiency. We propose three new techniques to develop a novel SRAM structure to realize multi-bit multiplication with bi-serial in/near memory computing. Firstly, we use 2-bit binary numbers (bi-serial) as the smallest unit of operation working in the mixed-signal mode to achieve arbitrary precision. This significantly reduces latency compared to the pure serial approaches. Secondly, we take the unique advantages of bi-serial (2-bit by 2-bit) multiplication and reduce the number of voltage bands that we need to differentiate from seven to four. This reduces the voltage swing on analog bit-lines (ABLs), in this way, reducing the dynamic power and improving accuracy. Thirdly, we optimize a low-cost voltage comparator based on the inverter chain to reduce static power further. When normalized to 8-bit by 8-bit multiply operation and implemented a 16KB SRAM array in SMIC 55-nm CMOS technology, the energy efficiency of our design is 1.47 TOPS/W, which is 2.7 times better than the state-of-the-art. © 2020 IEEE