ShanghaiTech University Knowledge Management System
Exploring Architectural Implications to Boost Performance forin-NVM B+-tree | |
2023-01 | |
会议录名称 | 28TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE |
发表状态 | 正式接收 |
摘要 | Computer architecture keeps evolving to support the byte-addressablenon-volatile memory (NVM). Researchers have tailored the preva-lent B+-tree with NVM, crafting a history of utilizing architecturalsupports to gain both high performance and crash consistency. Thelatest architecture-level changes for NVM, e.g., the eADR, moti-vate us to further explore architectural implications in the designand implementation of in-NVM B+-tree. Our quantitative studyfinds that eADR makes the cache misses impact increasingly on anin-NVM B+-tree’s performance. We hence propose Conan for theconflict-awarenodeallocationbased on theoretical justifications.Conan decomposes the virtual addresses of B+-tree nodes regardinga VIPT cache and intentionally places them into different cache sets.Experiments show that Conan evidently reduces cache conflictsand boosts the performance of state-of-the-art in-NVM B+-tree. |
文献类型 | 会议论文 |
条目标识符 | https://kms.shanghaitech.edu.cn/handle/2MSLDSTB/241127 |
专题 | 信息科学与技术学院_硕士生 信息科学与技术学院_PI研究组_王春东组 |
作者单位 | ShanghaiTech University |
第一作者单位 | 上海科技大学 |
第一作者的第一单位 | 上海科技大学 |
推荐引用方式 GB/T 7714 | Yanpeng Hu,Qisheng Jiang,Chundong Wang. Exploring Architectural Implications to Boost Performance forin-NVM B+-tree[C],2023. |
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