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JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits
会议论文
2024 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), Valencia, Spain, 25-27 March 2024
作者:
Siyan Chen
;
Rongliang Fu
;
Junying Huang
;
Zhimin Zhang
Adobe PDF(654Kb)
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收藏
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浏览/下载:217/0
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提交时间:2024/06/17
Alignment
Computation theory
Computer circuits
Computing power
Dynamic programming
Heuristic methods
Timing circuits
Computing technology
Length matching
Low-power consumption
Placement
Rapid single flux quantum circuits
Rapid single-flux quantum logic
Rapid single-flux-quantum
Superconducting logic
Timing alignment
Wire length
JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits
会议论文
PROCEEDINGS OF THE ACM GREAT LAKES SYMPOSIUM ON VLSI, GLSVLSI, Knoxville, TN, United states, June 5, 2023 - June 7, 2023
作者:
Chen, Xinda
;
Fu, Rongliang
;
Huang, Junying
;
Cao, Huawei
;
Zhang, Zhimin
Adobe PDF(1863Kb)
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收藏
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浏览/下载:335/0
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提交时间:2023/07/14
Computation theory
Computer circuits
Energy efficiency
Timing circuits
Length matching
Manhattan routing
Multi terminals
Rapid single flux quantum circuits
Rapid single-flux quantum logic
Rapid single-flux-quantum
Routing model
Routings
Rsfq
Superconducting logic
Mixed-Type Wafer Failure Pattern Recognition
会议论文
PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC, Tokyo, Japan, January 16, 2023 - January 19, 2023
作者:
Geng, Hao
;
Sun, Qi
;
Chen, Tinghuan
;
Xu, Qi
;
Ho, Tsung-Yi
Adobe PDF(2023Kb)
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收藏
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浏览/下载:261/2
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提交时间:2023/03/10
Failure (mechanical)
Silicon wafers
Complex circuits
Defect patterns
Failure mechanism
Failure patterns
In-process
Mixed type
Reduce time
Technology nodes
Time to market
Yield rates
Semiconductor device modeling
Art
Federated learning
Statistical distributions
Feature extraction
Foundries
Data models
Mixed-Type Wafer Failure Pattern Recognition (Invited Paper)
会议论文
2023 28TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), Tokyo, Japan, 16-19 Jan. 2023
作者:
Hao Geng
;
Qi Sun
;
Tinghuan Chen
;
Qi Xu
;
Tsung-Yi Ho
Adobe PDF(1271Kb)
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收藏
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浏览/下载:95/1
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提交时间:2024/09/18
PPATuner: Pareto-driven Tool Parameter Auto-tuning in Physical Design via Gaussian Process Transfer Learning
会议论文
PROCEEDINGS OF THE 59TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, San Francisco, July 10–14
作者:
Hao Geng
;
Qi Xu
;
Tsung-Yi Ho
;
Bei Yu
Adobe PDF(1903Kb)
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收藏
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浏览/下载:213/0
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提交时间:2023/03/20
EDA
Tool Parameter Tuning
Gaussian Process
Transfer Learning
Active Learning
How Secure Is Split Manufacturing in Preventing Hardware Trojan?
期刊论文
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2020, 卷号: 25, 期号: 2, 页码: 1-23
作者:
Yajun,Yang
;
Zhang,Chen
;
Yuan,Liu
;
Tsung-Yi,Ho
;
Yier,Jin
Adobe PDF(2065Kb)
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浏览/下载:315/3
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提交时间:2021/05/30
How Secure is Split Manufacturing in Preventing Hardware Trojan?
会议论文
PROCEEDINGS OF THE 2016 IEEE ASIAN HARDWARE ORIENTED SECURITY AND TRUST SYMPOSIUM (ASIANHOST 2016), Yilan, 19-20 Dec. 2016
作者:
Chen, Zhang
;
Zhou, Pingqiang
;
Ho, Tsung-Yi
;
Jin, Yier
Adobe PDF(732Kb)
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收藏
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浏览/下载:439/0
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提交时间:2017/07/04
Logic gates
Layout
Manufacturing
Security
Foundries
Metals
Hardware
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