上海科技大学知识管理系统

This article presents a fractional-N cascaded phaselocked loop (PLL) employing a calibration-free noise-and-spur cancellation technique. By incorporating an over-sampling cancellation path, the proposed architecture suppresses both the noise and spurs from the 1st-stage RO-based frequency multiplier without requiring high-reference frequency or calibration. A proof-of-concept prototype fabricated in 28-nm CMOS technology demonstrates 127.8 fs rms jitter (integrated from 10 KHz to 100MHz) with 4.48 mW power consumption, achieving a figure of merit (FoM) of -251.4 dB. The implemented cancellation technique decreases both the in-band phase noise (PN) and fractional spurs by over 20 dB, reaching levels of -113 dBc/Hz at a 1 MHz offset and -62dBc respectively.