上海科技大学知识管理系统

In this work, we propose an explicit-data-reuse neural rendering (EDR-NR) architecture to deliver high-throughput, energy-area-efficient photo-realistic rendering on edge devices. The EDR-NR chip is fabricated in 40nm CMOS technology and occupies 10.5 mm2 . Operating at 380MHz, EDR-NR is capable of rendering 800×800 resolution scenes at 85.9 FPS with 643.5 mW power dissipation, translating to 11.7 nJ/pixel. Our EDR-NR achieves 2.25× normalized throughput and 1.32×energy-efficiency improvements compared to state-ofthe-art NR processors, even though it is implemented in an older CMOS technology node.