上海科技大学知识管理系统

High-Level Synthesis (HLS) enables software engineers to create in tricate digital circuit designs using high-level languages like C/C++. While HLS tools can perform functional verification using C/C++ simulation, it is harder to verify that the generated RTL is also cor rect. This problem is exacerbated for designs which include HLS generated IPs, such as PCIe or DDR interfaces, or hand-written RTL. While it is possible to perform cycle-accurate verification using C/RTL co-simulation, conventional methods are both slow and typically only focus on unit-level verification which can make it harder to identify the root cause of a bug. To improve hardware verification, we propose Hercules: a novel method to efficiently verify HLS designs while preserving fine grained debugging capabilities. HLS-generated hardware and cor responding C/C++ software models are run simultaneously on the FPGA’s programmable logic and hardened processors respectively. Wecompare both results of the hardware and software, and also compare internal signals with the help of the automatically gener ated probes to identify bugs and their root causes. This capability is embedded within a tool that takes hardware snapshots, meaning to debug the design we can recreate a software simulation from a point shortly before where the bug occurred. With Hercules, we have performed verification quickly over large benchmarks. This has helped us find HLS errors closer to their root cause than existing tools, making it easier to debug, as well as identify real issues in existing benchmarks and the Vitis HLS tool which current state-of-the-art methods were unable to locate. Moreover, it achieves this quickly- over a set of HLS benchmarks Hercules achieves speedups with a geometric mean ranging from 1391× to 8060× compared to conventional software simulations.