Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization

doi:10.1145/3659950

	Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization
	Chen, Tinghuan 1; Geng, Hao2 ; Sun, Qi 3; Wan, Sanping 4; Sun, Yongsheng 5; Yu, Huatao 4; Yu, Bei 6
	2024-08-01
发表期刊	ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS (IF:2.2[JCR-2023],1.7[5-Year])
ISSN	1084-4309
EISSN	1557-7309
卷号	29 期号:5
发表状态	已发表
DOI	10.1145/3659950
摘要	Transistor aging leads to the deterioration of analog circuit performance over time. The worst aging degradation is used to evaluate the circuit reliability. It is extremely expensive to obtain it since several circuit stimuli need to be simulated. The worst degradation collection cost reduction brings an inaccurate training dataset when a machine learning (ML) model is used to fast perform the estimation. Motivated by the fact that there are many similar subcircuits in large-scale analog circuits, in this article we propose Wages to train an ML model on an inaccurate dataset for the worst aging degradation estimation via a domain generalization technique. A sampling-based method on the feature space of the transistor and its neighborhood subcircuit is developed to replace inaccurate labels. A consistent estimation for the worst degradation is enforced to update model parameters. Label updating and model updating are performed alternately to train an ML model on the inaccurate dataset. Experimental results on the very advanced 5nm technology node show that our Wages can significantly reduce the label collection cost with a negligible estimation error for the worst aging degradations compared to the traditional methods.
关键词	Analog circuits aging reliability machine learning
URL	查看原文
收录类别	EI ; SCI
语种	英语
资助项目	National Key R&D Program of China[2023YFB4402900] ; Research Grants Council of Hong Kong SAR[CUHK14208021] ; National Natural Science Foundation of China[62304197] ; Shanghai Pujiang Program[22PJ1410400]
WOS研究方向	Computer Science
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Software Engineering
WOS记录号	WOS:001332630700007
出版者	ASSOC COMPUTING MACHINERY
EI入藏号	20244217205459
EI主题词	Electric network analysis
EI分类号	703.1.1 Electric Network Analysis
原始文献类型	Journal article (JA)
文献类型	期刊论文
条目标识符	https://kms.shanghaitech.edu.cn/handle/2MSLDSTB/436533
专题	信息科学与技术学院信息科学与技术学院_PI研究组_耿浩
通讯作者	Chen, Tinghuan
作者单位	1.School of Science and Engineering, The Chinese University of Hong Kong-Shenzhen, Shenzhen, China; 2.School of Information Science and Technology, ShanghaiTech University, Shanghai, China; 3.College of Integrated Circuits, Zhejiang University, Zhejiang, Hangzhou, China; 4.HiSilicon Technologies Co., Shenzhen, China; 5.HiSilicon Technologies Co., Chengdu, China; 6.Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong
推荐引用方式 GB/T 7714	Chen, Tinghuan,Geng, Hao,Sun, Qi,et al. Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization[J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,2024,29(5).
APA	Chen, Tinghuan.,Geng, Hao.,Sun, Qi.,Wan, Sanping.,Sun, Yongsheng.,...&Yu, Bei.(2024).Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization.ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,29(5).
MLA	Chen, Tinghuan,et al."Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization".ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 29.5(2024).