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Ultra-Fast FPGA Implementation of Graph Cut Algorithm With Ripple Push and Early Termination
期刊论文
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022
Authors:
Yan, Guangyao
;
Liu, Xinzhe
;
Chen, Fupeng
;
Wang, Hui
;
Ha, Yajun
Adobe PDF(2732Kb)
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View/Download:39/0
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Submit date:2022/01/18
Parallel processing
Field programmable gate arrays
Task analysis
Irrigation
Computer vision
Real-time systems
Information science
Graph cut
maximum flow
minimum cut
ripple push
early termination
hardware-friendly
ultra-fast
FPGA implementation
FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA
期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022
Authors:
Jiang, Weixiong
;
Yu, Heng
;
Zhang, Hongtu
;
Shu, Yuhao
;
Li, Rui
Adobe PDF(4417Kb)
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View/Download:26/0
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Submit date:2022/02/14
Delays
Registers
Monitoring
Field programmable gate arrays
Clocks
Voltage measurement
Temperature measurement
Circuits and systems
digital circuits
digital integrated circuits
Incoming Editorial
期刊论文
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, 2022, 卷号: 69, 期号: 1, 页码: 2-4
Authors:
Ha, Yajun
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View/Download:2/0
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Submit date:2022/05/20
A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations
期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022
Authors:
Chen, Jian
;
Zhao, Wenfeng
;
Wang, Yuqi
;
Shu, Yuhao
;
Jiang, Weixiong
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View/Download:0/0
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Submit date:2022/05/13
Associative storage
Computation theory
Integrated circuit design
Integrated circuits
Memory architecture
Reliability
Static random access storage
Timing circuits
Content addressable memory
Content-addressable memory
High Speed
In-memory computing
Integrated circuit reliability
Logic in memory
Memory operations
Random access memory
Read disturbance
SRAM.
可用于人工智能物联网的高能效二值神经网络加速器
专利
申请号:CN202111169933.X,申请日期: 2021-10-08,类型:发明申请,状态:实质审查
Inventors:
张宏图
;
束宇豪
;
哈亚军
Adobe PDF(1661Kb)
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View/Download:44/0
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Submit date:2022/01/14
一种用于卷积神经网络的内存计算eDRAM加速器
专利
申请号:CN202111169936.3,申请日期: 2021-10-08,类型:发明申请,状态:实质审查
Inventors:
张宏图
;
束宇豪
;
哈亚军
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View/Download:39/0
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Submit date:2022/01/18
CLIF: Cross-layer information fusion for stereo matching and its hardware implementation
会议论文
PROCEEDINGS - IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, Daegu, Korea, Republic of, May 22, 2021 - May 28, 2021
Authors:
Chen, Fupeng
;
Liu, Xinzhe
;
Yu, Heng
;
Ha, Yajun
Adobe PDF(1078Kb)
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View/Download:28/0
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Submit date:2021/12/03
Intelligent systems
Hardware implementations
Implicit informations
Information sharing strategies
Local stereo matching
Performance impact
Pipelined hardware
Regularization terms
Stereo matching algorithm
A fault resistant AES via input-output differential tables with DPA awareness
会议论文
PROCEEDINGS - IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, Daegu, Korea, Republic of, May 22, 2021 - May 28, 2021
Authors:
Wang, Yi
;
Stöttinger, Marc
;
Ha, Yajun
Adobe PDF(1126Kb)
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Submit date:2021/12/03
Fault detection
Convergence speed
Detection methods
Differential fault analyses (DFA)
Differential power Analysis
Fault coverages
Fault injection
Implementation architecture
Information leakage
用于无人驾驶中激光点云定位的正态分布变换方法
专利
申请号:CN202110718013.2,申请日期: 2021-06-28,类型:发明申请,状态:实质审查
Inventors:
邓岂
;
孙豪
;
哈亚军
;
汪辉
Adobe PDF(652Kb)
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View/Download:30/1
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Submit date:2021/10/24
An optimized reconfiguration algorithm based on DVFS
专利
申请号:WOCN21099124,申请日期: 2021-06-09,类型:发明申请,状态:未进入国家阶段-PCT有效期内
Inventors:
LI Rui
;
HA Yajun
Unknown(1296Kb)
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View/Download:25/0
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Submit date:2022/01/25