A 4-to-16GHz Dual-Loop PLL Based on Current-Control RO and Calibration in a 6-nm FinFET

doi:10.1109/ICCCAS62034.2024.10652768

	A 4-to-16GHz Dual-Loop PLL Based on Current-Control RO and Calibration in a 6-nm FinFET
	Jiangting Xia1,2 ; Xi-An Wu 2,3; Tong Tian1,2
	2024
会议录名称	2024 13TH INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS (ICCCAS)
页码	195-199
发表状态	已发表
DOI	10.1109/ICCCAS62034.2024.10652768
摘要	This work presents a PLL design in an advanced 6- nm FinFET CMOS technology and proposes a strategy for designing a ring-based PLL with low jitter and reference spur performance. With calibration function, the ring-based PLL achieves 420−fsrms integrated jitter and reference spurs at -68 dBc, which can meet the low noise requirements of 32Gbps SerDes. The PLL has an active area of 0.015 mm2, consuming 4.9 mW from a 0.75V supply at 16GHz, translating to a figure of merit of -240.6 dB.
会议录编者/会议主办者	IEEE
关键词	oscillator frequency synthesizer PLL calibration jitter
会议名称	13th IEEE International Conference on Communications, Circuits, and Systems, ICCCAS 2024
会议地点	Xiamen, China
会议日期	10-12 May 2024
URL	查看原文
收录类别	EI
语种	英语
出版者	Institute of Electrical and Electronics Engineers Inc.
EI入藏号	20243817079286
EI主题词	FinFET
EI分类号	1106.3 ; 713.2 Oscillators ; 714.2 Semiconductor Devices and Integrated Circuits ; 716.1 Information Theory and Signal Processing ; 904
原始文献类型	Conference article (CA)
来源库	IEEE
引用统计	正在获取...
文献类型	会议论文
条目标识符	https://kms.shanghaitech.edu.cn/handle/2MSLDSTB/418531
专题	信息科学与技术学院_硕士生信息科学与技术学院_特聘教授组_田彤组
通讯作者	Tong Tian
作者单位	1.ShanghaiTech University 2.Shanghai Institute of Microsystem and Information Technology 3.University of Chinese Academy of Sciences
第一作者单位	上海科技大学
通讯作者单位	上海科技大学
第一作者的第一单位	上海科技大学
推荐引用方式 GB/T 7714	Jiangting Xia,Xi-An Wu,Tong Tian. A 4-to-16GHz Dual-Loop PLL Based on Current-Control RO and Calibration in a 6-nm FinFET[C]//IEEE:Institute of Electrical and Electronics Engineers Inc.,2024:195-199.