节能FPGA实现的无序并行最大流//最小割方法

	节能FPGA实现的无序并行最大流//最小割方法
翻译题名	DISORDERED PARALLEL MAXIMUM FLOW//MINIMUM CUT METHOD IMPLEMENTED BY ENERGY-EFFICIENT FIELD-PROGRAMMABLE GATE ARRAY (FPGA)
申请号	US18401731
	2024-08-15
公开（公告）号	US20240273273A1
公开日期	2024-08-15
摘要	一种高效节能的FPGA实现的无序并行最大流//最小割方法，将单层大的二维网格图折叠成多层小的网格图。该方法使得折叠网格架构能够存储和处理尺寸比处理器阵列大得多的网格图。所述折叠网格架构赋予二维处理器阵列在垂直方向上的自由度，使得所述二维处理器阵列可以基于所述垂直方向上的自由度来利用所述折叠网格架构的并行性能的潜力。折叠网格架构使得小尺寸处理器阵列能够具有处理网格图的能力，该网格图在尺寸上比小尺寸处理器阵列大得多。此外，基于折叠的轴对称性，折叠网格架构可以大大减少处理器阵列中数据的跨界传输。
翻译摘要	A disordered parallel maximum flow//minimum cut method implemented by an energy-efficient field-programmable gate array (FPGA) folds a single-layer large two-dimensional grid graph into a multi-layer small grid graph. The method enables a folding grid architecture to store and process a grid graph that is much larger than a processor array in size. The folding grid architecture endows a two-dimensional processor array with a degree of freedom in a vertical direction, such that the two-dimensional processor array can leverage a potential for parallel performance of the folding grid architecture based on the degree of freedom in the vertical direction. The folding grid architecture enables a small-sized processor array to have an ability to process a grid graph that is much larger than the small-sized processor array in size. In addition, based on axial symmetry of folding, the folding grid architecture can greatly reduce cross-boundary transmission of data in the processor array.
当前权利人	Shanghaitech University
专利申请人	Shanghaitech University
	Guangyao Yan; Xinzhe Liu; Yajun Ha; Hui Wang
公开国别	美国
公开国别简称	US
IPC 分类号	G06F30//347; G06F30//392; G06F111//10; G06F115//10
CPC分类号	G06F30//347; G06F30//392; G06F2111//10; G06F2115//10
专利有效性	审中
专利类型	发明申请
专利类型字典	1
当前法律状态	实质审查
简单同族	US20240273273A1; CN116302495A
扩展同族	US20240273273A1; CN116302495A
INPADOC 同族	US20240273273A1
文献类型	专利
条目标识符	https://kms.shanghaitech.edu.cn/handle/2MSLDSTB/408386
专题	信息科学与技术学院_特聘教授组_汪辉组信息科学与技术学院_PI研究组_哈亚军组信息科学与技术学院_博士生
作者单位	Shanghaitech University
推荐引用方式 GB/T 7714	Guangyao Yan,Xinzhe Liu,Yajun Ha,等. 节能FPGA实现的无序并行最大流//最小割方法. US18401731[P]. 2024-08-15.