上海科技大学知识管理系统

本发明的技术方案是提供了一种比特交错结构下可消除半选择干扰的超低电压SRAM单元，其特征在于，包括一组反相器环，两个N型写晶体管NM1、NM2，两个P型写晶体管PM1、PM2和两个N型晶体管NM3、NM4组成的读出路径。本发明可以被应用于超低电压有存储需求的应用中，特别是一些对于低电压下SRAM访存速度及可靠性有一定需求的应用，相比其他不同SRAM单元，在能耗相差不大的情况下，本发明可以实现更高的读写工作频率。

A technical solution of the present invention provides an ultra-low voltage SRAM unit capable of eliminating half-select disturbance in a bit-interleaved structure, characterized by comprising a read path composed of a set of inverter rings, two N-type write transistors NM1 and NM2, two P-type write transistors PM1 and PM2, and two N-type transistors NM3 and NM4. The present invention can be applied to ultra-low voltage applications having storage requirements, and in particular to applications having particular requirements for SRAM access speed and the reliability at a low voltage. Compared with other SRAM units, the present invention can achieve very high read and write operating frequencies while maintaining a low energy consumption difference.