上海科技大学知识管理系统

本发明公开了一种低温高能效存内计算加速器。本发明的创新之处在于：高保留时间的低温3T存储单元设计：本发明提出了一种基于eDRAM的低温3T存储单元设计，它可以在没有任何字线电压提升方案的情况下显著提升保留时间，在写操作过程中实现全摆幅数据传输。低温自适应可重构灵敏放大器设计：本发明开发了一种低温片上自适应可重构灵敏放大器设计，通过配置ARSA的参考电压，可以实现片上精确的布尔逻辑计算。低温优化的FlashADC设计：本发明使用所设计的ARSA，在片上自适应产生15个ARSA的参考电压，并重构为4bit Flash ADC。通过片上的自适应配置参考电压以及存储方式，该设计可以确保快速且低功耗卷积计算实现。

Disclosed in the present invention is a cryogenic high-energy-efficiency computing-in-memory accelerator. The innovations of the present invention lie in : the design of a long-retention-time cryogenic 3T storage unit : provided in the present invention is the design of an eDRAM-based cryogenic 3T storage unit, which can significantly increase a retention time without any word line voltage boosting solution, and realize full-swing data transmission during a write operation process; the design of a cryogenic adaptive reconfigurable sense amplifier (ARSA) : developed in the present invention is the design of a cryogenic on-chip ARSA, which can realize accurate Boolean logic calculation on a chip by means of configuring a reference voltage of the ARSA; and the design of a cryogenic optimized Flash ADC : in the present invention, the designed ARSA is used to adaptively generate reference voltages of fifteen ARSAs on a chip, and reconstruct the fifteen ARSAs into a 4-bit Flash ADC. By means of adaptively configured reference voltages and a storage mode on a chip, the design can guarantee the implementation of rapid and low-power-consumption convolution calculation.