A Bin-by-Bin Calibration with Neural Network for FPGA-Based Tapped-Delay-Line Time-to-Digital Converter

doi:10.1109/RCAR54675.2022.9872281

	A Bin-by-Bin Calibration with Neural Network for FPGA-Based Tapped-Delay-Line Time-to-Digital Converter
	Yue Xu 1; Jie Xie 1; Zhiwei Xing 2; Wenqiang Yuan 1; Guanqun Yu3 ; Zhongmin Zeng 1; Baoshun Zhang 1; Dongmin Wu 1
	2022-07
会议录名称	2022 IEEE INTERNATIONAL CONFERENCE ON REAL-TIME COMPUTING AND ROBOTICS (RCAR)
发表状态	已发表
DOI	10.1109/RCAR54675.2022.9872281
摘要	The method of implementing TDC with FPGA carry chain is widely used, but the delay time of each TDC bin is greatly affected by the changes of operating temperature. At present, the commonly used methods can’t well fit the changing trend of each delay bin in long delay line under the influence of complex temperature changes. In this paper, a neural network calibration module based on MLP is proposed, in which 128 delay time data of delay line and corresponding temperature data transmitted to the host computer are used as training samples to establish MLP. When working, the delay time of each TDC bin can be given independently by knowing current temperature condition. Through experiments, the compensation of network calibration module on temperature changes is verified, and the network can be transplanted to different types of FPGA chips and run under various temperature changes. The TDC have a precision of 34ps.
关键词	Training Temperature distribution Neural networks Delay lines Mathematical models Time measurement Calibration
会议地点	Guiyang, China
会议日期	17-22 July 2022
URL	查看原文
来源库	IEEE
文献类型	会议论文
条目标识符	https://kms.shanghaitech.edu.cn/handle/2MSLDSTB/354959
专题	物质科学与技术学院物质科学与技术学院_硕士生
作者单位	1.Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences, Suzhou, China 2.Harbin Institute of Technology, Shenzhen, China 3.School of Physical Science and Technology, Shanghaitech University, Shanghai, China
推荐引用方式 GB/T 7714	Yue Xu,Jie Xie,Zhiwei Xing,et al. A Bin-by-Bin Calibration with Neural Network for FPGA-Based Tapped-Delay-Line Time-to-Digital Converter[C],2022.