A Read Margin Enhancement Circuit With Dynamic Bias Optimization for MRAM

doi:10.1109/TCSII.2024.3367988

	A Read Margin Enhancement Circuit With Dynamic Bias Optimization for MRAM
	Chen, Renhe1 ; Lee, Albert 2; Wang, Zirui1 ; Wu, Di 2; Kou, Xufeng1
	2024
发表期刊	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS (IF:4.0[JCR-2023],3.7[5-Year])
ISSN	1558-3791
EISSN	1558-3791
卷号	PP 期号:99 页码:3905-3909
发表状态	已发表
DOI	10.1109/TCSII.2024.3367988
摘要	This brief introduces a read bias circuit to improve readout yield of magnetic random access memories (MRAMs). A dynamic bias optimization (DBO) circuit is proposed to enable the real-time tracking of the optimal read voltage across MRAM process variations and operating temperature fluctuation within an MRAM array. It optimizes read performance by adjusting the read bias voltage dynamically for maximum sensing margin. Simulation results on a 28-nm 1Mb MRAM macro show that the tracking accuracy of the proposed DBO circuit remains above 90% even when the optimal sensing voltage varies up to 50%. Such dynamic tracking strategy further results in up to two orders of magnitude reduction in the bit error rate with respect to different variations, highlighting its effectiveness in enhancing MRAM performance and reliability.
关键词	Magnetic random access memory read margin enhancement tunneling magnetoresistance ratio readout mechanism bias voltage optimization
URL	查看原文
收录类别	EI ; SCI
语种	英语
资助项目	National Key Research and Development Program of China[2021YFA0715503] ; National Natural Science Foundation of China[92164104] ; Shanghai Rising-Star Program[21QA1406000]
WOS研究方向	Engineering
WOS类目	Engineering, Electrical & Electronic
WOS记录号	WOS:001283904700067
出版者	Institute of Electrical and Electronics Engineers Inc.
EI入藏号	20240915653028
EI主题词	Bias voltage
EI分类号	701.2 Magnetism: Basic Concepts and Phenomena ; 713 Electronic Circuits ; 722.1 Data Storage, Equipment and Techniques ; 723.1 Computer Programming
原始文献类型	Journal article (JA)
来源库	IEEE
文献类型	期刊论文
条目标识符	https://kms.shanghaitech.edu.cn/handle/2MSLDSTB/346059
专题	信息科学与技术学院_硕士生信息科学与技术学院_PI研究组_寇煦丰组
通讯作者	Kou, Xufeng
作者单位	1.ShanghaiTech University 2.Inston Tech
第一作者单位	上海科技大学
通讯作者单位	上海科技大学
第一作者的第一单位	上海科技大学
推荐引用方式 GB/T 7714	Chen, Renhe,Lee, Albert,Wang, Zirui,et al. A Read Margin Enhancement Circuit With Dynamic Bias Optimization for MRAM[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS,2024,PP(99):3905-3909.
APA	Chen, Renhe,Lee, Albert,Wang, Zirui,Wu, Di,&Kou, Xufeng.(2024).A Read Margin Enhancement Circuit With Dynamic Bias Optimization for MRAM.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS,PP(99),3905-3909.
MLA	Chen, Renhe,et al."A Read Margin Enhancement Circuit With Dynamic Bias Optimization for MRAM".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS PP.99(2024):3905-3909.