Hercules: Enabling Atomic Durability for Persistent Memory with Transient Persistence Domain

doi:10.1145/3607473

	Hercules: Enabling Atomic Durability for Persistent Memory with Transient Persistence Domain
	YE, CHONGNAN1,2 ; CHEN, MENG1,2 ; JIANG, QISHENG1,2 ; WANG, CHUNDONG1,2
	2023
发表期刊	ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS (TECS)
ISSN	1539-9087
EISSN	1558-3465
卷号	23 期号:6
发表状态	已发表
DOI	10.1145/3607473
摘要	Persistent memory (pmem) products bring the persistence domain up to the memory level. Intel recently introduced the eADR feature that guarantees to flush data buffered in CPU cache to pmem on a power outage, thereby making the CPU cache a transient persistence domain. . Researchers have explored how to enable the atomic durability for applications' in-pmem data. In this article, we exploit the eADR-supported CPU cache to do so. A modified cache line, until written back to pmem, is a natural redo log copy of the in-pmem data. However, a write-back due to cache replacement or eADR on a crash overwrites the original copy. We accordingly developed Hercules, a hardware logging design for the transaction-level atomic durability, with supportive components installed in CPU cache, memory controller (MC), and pmem. When a transaction commits, Hercules commits on-chip its data staying in cache lines. For cache lines evicted before the commit, Hercules asks the MC to redirect and persist them into in-pmem log entries and commits them off-chip upon committing the transaction. Hercules lazily conducts pmem writes only for cache replacements at runtime. On a crash, Hercules saves metadata and data for active transactions into pmem for recovery. Experiments show that, by using CPU cache for both buffering and logging, Hercules yields much higher throughput and incurs significantly fewer pmem writes than state-of-the-art designs.
关键词	Atomic durability persistent memory transient persistence domain
URL	查看原文
收录类别	SCIE ; SCI ; EI
语种	英语
WOS研究方向	Computer Science
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Software Engineering
WOS记录号	WOS:001325890900003
出版者	ASSOC COMPUTING MACHINERY
EI入藏号	20244017150612
EI主题词	Cache memory
EI分类号	1103.1 ; 1106.1 ; 701 Electricity and Magnetism
原始文献类型	Journal article (JA)
文献类型	期刊论文
条目标识符	https://kms.shanghaitech.edu.cn/handle/2MSLDSTB/331091
专题	信息科学与技术学院_硕士生信息科学与技术学院_PI研究组_王春东组
通讯作者	WANG, CHUNDONG
作者单位	1.School of Information Science and Technology, ShanghaiTech University, China 2.Shanghai Engineering Research Center of Energy Efficient and Custom AI IC, China
第一作者单位	信息科学与技术学院
通讯作者单位	信息科学与技术学院
第一作者的第一单位	信息科学与技术学院
推荐引用方式 GB/T 7714	YE, CHONGNAN,CHEN, MENG,JIANG, QISHENG,et al. Hercules: Enabling Atomic Durability for Persistent Memory with Transient Persistence Domain[J]. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS (TECS),2023,23(6).
APA	YE, CHONGNAN,CHEN, MENG,JIANG, QISHENG,&WANG, CHUNDONG.(2023).Hercules: Enabling Atomic Durability for Persistent Memory with Transient Persistence Domain.ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS (TECS),23(6).
MLA	YE, CHONGNAN,et al."Hercules: Enabling Atomic Durability for Persistent Memory with Transient Persistence Domain".ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS (TECS) 23.6(2023).