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Exploring Architectural Implications to Boost Performance for in-NVM B+-Tree | |
2023-01-16 | |
会议录名称 | PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC |
ISSN | 2153-6961 |
页码 | 116-121 |
发表状态 | 已发表 |
DOI | 10.1145/3566097.3567861 |
摘要 | Computer architecture keeps evolving to support the byte-addressable non-volatile memory (NVM). Researchers have tailored the prevalent B+-tree with NVM, crafting a history of utilizing architectural supports to gain both high performance and crash consistency. The latest architecture-level changes for NVM, e.g., the eADR, motivate us to further explore architectural implications in the design and implementation of in-NVM B+-tree. Our quantitative study finds that eADR makes the cache misses impact increasingly on an in-NVM B+-tree's performance. We hence propose Conan for the co nflict-aware n ode a llocation based on theoretical justifications. Conan decomposes the virtual addresses of B+-tree nodes regarding a VIPT cache and intentionally places them into different cache sets. Experiments show that Conan evidently reduces cache conflicts and boosts the performance of state-of-the-art in-NVM B+-tree. © 2023 Copyright held by the owner/author(s). |
会议录编者/会议主办者 | ACM SIGDA ; IEEE CAS ; IEEE CEDA ; IEICE ; IPS |
关键词 | Cache memory Memory architecture Nonvolatile storage Architectural support B trees Cache Miss Design and implementations Level change Non-volatile memory Performance Quantitative study Tree nodes VIPT cache |
会议名称 | 28th Asia and South Pacific Design Automation Conference, ASP-DAC 2023 |
会议地点 | Tokyo, Japan |
会议日期 | January 16, 2023 - January 19, 2023 |
URL | 查看原文 |
收录类别 | EI ; SCOPUS |
语种 | 英语 |
出版者 | Institute of Electrical and Electronics Engineers Inc. |
EI入藏号 | 20230813628042 |
EI主题词 | Virtual addresses |
EI分类号 | 722 Computer Systems and Equipment ; 722.1 Data Storage, Equipment and Techniques |
原始文献类型 | Conference article (CA) |
来源库 | IEEE |
文献类型 | 会议论文 |
条目标识符 | https://kms.shanghaitech.edu.cn/handle/2MSLDSTB/282082 |
专题 | 信息科学与技术学院 信息科学与技术学院_硕士生 信息科学与技术学院_博士生 信息科学与技术学院_PI研究组_王春东组 |
作者单位 | School of Information Science and Technology, ShanghaiTech University, China |
第一作者单位 | 信息科学与技术学院 |
第一作者的第一单位 | 信息科学与技术学院 |
推荐引用方式 GB/T 7714 | Yanpeng Hu,Qisheng Jiang,Chundong Wang. Exploring Architectural Implications to Boost Performance for in-NVM B+-Tree[C]//ACM SIGDA, IEEE CAS, IEEE CEDA, IEICE, IPS:Institute of Electrical and Electronics Engineers Inc.,2023:116-121. |
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