AOS: An Automated Overclocking System for High Performance CNN Accelerator Through Timing Delay Measurement on FPGA

doi:10.1109/TCAD.2023.3235803

	AOS: An Automated Overclocking System for High Performance CNN Accelerator Through Timing Delay Measurement on FPGA
	Weixiong Jiang1 ; Heng Yu 2; Fupeng Chen1 ; Yajun Ha3
	2023
发表期刊	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (IF:2.7[JCR-2023],2.9[5-Year])
ISSN	0278-0070
EISSN	1937-4151
卷号	42 期号:9 页码:1-1
发表状态	已发表
DOI	10.1109/TCAD.2023.3235803
摘要	With the inherent algorithmic error resilience of conventional neural networks (CNN) and the worst-case design methodologies of current electronic design automation tools, overclocking-based timing speculation is a promising technique to improve the performance of CNN accelerators on FPGA by removing unnecessary timing margins. To avoid potential timing errors, timing delay measurement should be used during overclocking. However, current approaches are not yet good at measuring paths with more intense variability factors such as jitter, and lack an automated process for testing circuit delays. In this paper, we first propose 2-dimension multi-frame fusion to deal with the sampling jitter, then present a timing delay measurement-based automatic overclocking system (AOS) running on heterogeneous FPGA for high-performance CNN accelerators. On the FPGA side, AOS is composed of timing delay monitors (TDM) that can measure all types of timing paths, a TDM controller that converts the sampled values of TDMs into timing delay in terms of the ratio of path delay to the clock period. On the CPU side, AOS converts the path delay from clock period ratio to absolute delay value and decides the frequency of the accelerator in the next iteration. We demonstrate AOS with a SkyNet accelerator on the Xilinx ZCU104 board and achieve 657FPS at 436MHz without accuracy degradation, which is 1.41 performance compared to the baseline. IEEE
关键词	Automation Computer aided design Delay circuits Field programmable gate arrays (FPGA) Iterative methods Time division multiplexing Timing circuits Timing jitter Uncertainty analysis Delay Field programmable gate array Field programmables Measurement uncertainty Overclocking Performance Programmable gate array Register Time-division multiplexing Timing delay
URL	查看原文
收录类别	EI ; SCOPUS
语种	英语
出版者	Institute of Electrical and Electronics Engineers Inc.
EI入藏号	20230613542604
EI主题词	Clocks
EI分类号	713.4 Pulse Circuits ; 721.2 Logic Elements ; 723.5 Computer Applications ; 731 Automatic Control Principles and Applications ; 921.6 Numerical Methods ; 922.1 Probability Theory ; 943.3 Special Purpose Instruments
原始文献类型	Article in Press
来源库	IEEE
引用统计	正在获取...
文献类型	期刊论文
条目标识符	https://kms.shanghaitech.edu.cn/handle/2MSLDSTB/281989
专题	信息科学与技术学院信息科学与技术学院_PI研究组_哈亚军组信息科学与技术学院_博士生
通讯作者	Heng Yu; Yajun Ha
作者单位	1.School of Information Science and Technology, ShanghaiTech University, Shanghai, China 2.School of Computer Science, University of Nottingham Ningbo China, Ningbo, China 3.School of Information Science and Technology and the Shanghai Engineering Research Center of Energy Efficient and Custom AI IC, ShanghaiTech University, Shanghai, China
第一作者单位	信息科学与技术学院
通讯作者单位	信息科学与技术学院
第一作者的第一单位	信息科学与技术学院
推荐引用方式 GB/T 7714	Weixiong Jiang,Heng Yu,Fupeng Chen,et al. AOS: An Automated Overclocking System for High Performance CNN Accelerator Through Timing Delay Measurement on FPGA[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2023,42(9):1-1.
APA	Weixiong Jiang,Heng Yu,Fupeng Chen,&Yajun Ha.(2023).AOS: An Automated Overclocking System for High Performance CNN Accelerator Through Timing Delay Measurement on FPGA.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,42(9),1-1.
MLA	Weixiong Jiang,et al."AOS: An Automated Overclocking System for High Performance CNN Accelerator Through Timing Delay Measurement on FPGA".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 42.9(2023):1-1.