A 39pJ/label 1920x1080 165.7 FPS Block PatchMatch Based Stereo Matching Processor on FPGA

doi:10.1109/CICC53496.2022.9772830

	A 39pJ/label 1920x1080 165.7 FPS Block PatchMatch Based Stereo Matching Processor on FPGA
	Hongyu Wang; Wei Zhou; Xiangyu Zhang; Xin Lou
	2022
会议录名称	2022 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)
ISSN	0886-5930
发表状态	已发表
DOI	10.1109/CICC53496.2022.9772830
摘要	Depth is a fundamental information for lots of computer vision applications. Stereo matching is a commonly used depth estimation method that mimics the human binocular vision system. Most stereo matching systems suffer when attempt to strike a balance between accuracy and computational complexity because of two reasons: 1) It is usually assumed that all the surfaces are fronto-parallel, meaning that neighbors share the same disparity. But a lot of real-world situations are slant surfaces like roads and walls. 2) Conventional methods usually utilize winner takes all (WTA) strategy [1]–[4], where aggregated costs in all disparity levels (usually 128 or 256) must be calculated. But there is only one true guess for each pixel position, such that most of the calculated costs are meaningless. To solve the above issues, in this work, a block PatchMatch-based FPGA accelerator for stereo matching is proposed. PatchMatch introduces random search strategy and slant label, where rectangle superpixels called blocks are used as the basic computing element. Main improvements of this work are: 1) Utilized random search strategy and block level computation can save massive computation. 2) Closer-to-reality slant label improves accuracy. Moreover, plane slant is also helpful for following tasks like 3D reconstruction [5], but none of the existing hardware accelerators can provide this information. 3) Algorithm-hardware co-optimized 6-points Census feature and multi-scale propagation (MSP) are proposed. 4) Based on the testing results on industrial-level KITTI dataset, the real-time performance and energy efficiency of the proposed design outperform state-of-the-art FPGA and ASIC designs, with comparable accuracy.
关键词	Costs Three-dimensional displays Roads Machine vision MIMICs Search problems Real-time systems
会议地点	Newport Beach, CA, USA
会议日期	24-27 April 2022
URL	查看原文
收录类别	EI
EI入藏号	9772830
来源库	IEEE
文献类型	会议论文
条目标识符	https://kms.shanghaitech.edu.cn/handle/2MSLDSTB/185376
专题	信息科学与技术学院_博士生信息科学与技术学院_PI研究组_娄鑫组
作者单位	ShanghaiTech University
第一作者单位	上海科技大学
第一作者的第一单位	上海科技大学
推荐引用方式 GB/T 7714	Hongyu Wang,Wei Zhou,Xiangyu Zhang,et al. A 39pJ/label 1920x1080 165.7 FPS Block PatchMatch Based Stereo Matching Processor on FPGA[C],2022.