FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA

doi:10.1109/TVLSI.2022.3144321

	FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA
	Weixiong Jiang1,2,3 ; Heng Yu 4; Hongtu Zhang1,2,3 ; Yuhao Shu1,2,3 ; Rui Li1,2,3 ; Jian Chen1,2,3 ; Yajun Ha1,5
	2022-04-01
发表期刊	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN	1557-9999
卷号	30 期号:4
发表状态	已发表
DOI	10.1109/TVLSI.2022.3144321
摘要	Voltage and frequency scaling (VFS) has been widely used to improve energy efficiency, lifespan, and system reliability by converting conservative timing margins into $V_{\text {dd}}$ reduction. Along these lines, to investigate the potential implementation of VFS technique in exploring the timing margins under different voltages and frequencies, in situ or online circuit delay measurement is required to monitor all timing paths, which are usually ended with terminal registers. The previously reported online delay measurement approaches require the output of a terminal register to be measurable. However, some FPGA timing paths are ended with embedded hardcores such as DSPs or BRAMs. It is impossible to measure the output of the terminal register inside a hardcore. To address the issue, we propose an online delay monitor (ODM) that can accurately measure the delay of any type of timing path in real-time conditions. The ODM is mainly composed of two shadow registers and a phase-shifted clock. The shadow registers use a phase-shifted clock signal as the input and the output signal of the combinational logic as the clock. In addition, we present an automatic tool and its corresponding design flow (FODM) for inserting an ODM to monitor a path. Compared with the state-of-the-art, our experimental results indicate that the proposed method has the ability to accurately measure the delays online for all the potential timing paths, regardless of their path termination types. Moreover, we demonstrate an average measurement error of only 1.51% using eight floating-point operators at different voltages.
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收录类别	SCI ; EI ; SCIE
来源库	IEEE
引用统计	正在获取...
文献类型	期刊论文
条目标识符	https://kms.shanghaitech.edu.cn/handle/2MSLDSTB/154090
专题	信息科学与技术学院_博士生信息科学与技术学院_PI研究组_哈亚军组信息科学与技术学院_硕士生
作者单位	1.School of Information Science and Technology, ShanghaiTech University, Shanghai, China 2.Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China 3.University of Chinese Academy of Sciences, Beijing, China 4.School of Computer Science, University of Nottingham Ningbo China, Ningbo, China 5.Shanghai Engineering Research Center of Energy Efficient and Custom AI IC, Shanghai, China
第一作者单位	信息科学与技术学院
第一作者的第一单位	信息科学与技术学院
推荐引用方式 GB/T 7714	Weixiong Jiang,Heng Yu,Hongtu Zhang,et al. FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2022,30(4).
APA	Weixiong Jiang.,Heng Yu.,Hongtu Zhang.,Yuhao Shu.,Rui Li.,...&Yajun Ha.(2022).FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,30(4).
MLA	Weixiong Jiang,et al."FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 30.4(2022).