Temperature-Driven Gate Geometry Effects in Nanoscale Cryogenic MOSFETs
Wang, Zewei1,2,3; Tang, Zhidong4; Guo, Ao5; Luo, Xin5; Cao, Chengwei5; Yuan, Yumeng1,2,3; Zhang, Xiuhao4; Liu, Lingge4; Li, Jialun4; Cao, Yongfeng6; Shao, Qiming7; Hu, Shaojian5; Chen, Shoumian5; Zhao, Yuhang; Kou, Xufeng4
2020-05
Source PublicationIEEE ELECTRON DEVICE LETTERS
ISSN0741-3106
EISSN1558-0563
Volume41Issue:5Pages:661-664
Status已发表
DOI10.1109/LED.2020.2984280
Abstract

This paper presents experimental characterizations and device modeling on the nanoscale MOSFETs with 40 nm low-power CMOS technology. Systematic temperature-dependent ${I}_{D}$ - ${V}_{GS}$ results of NMOS/PMOS devices reveal that both the threshold voltage and the effective channel mobility exhibit strong correlations with the device size owning to the depletion region broadening around the gate channel at cryogenic temperatures. By taking the temperature-driven gate geometry effects into consideration, a generic physical model with universal fitting parameters is proposed to depict the transfer characteristics of all CMOS transistors across the device size chart, and further validations of the modified BSIM compact model might pave the way for an accurate design of cryogenic electronics applications.

KeywordLogic gates Semiconductor device modeling Threshold voltage MOSFET Temperature measurement Cryogenic electronics effective mobility threshold voltage gate geometry effects
Indexed BySCI ; EI
Funding ProjectNational Key Research and Development Program of China[2017YFA0305400] ; National Natural Science Foundation of China[61874172] ; Strategic Priority Research Program of Chinese Academy of Sciences[XDA18010000] ; Shanghai Sailing Program[17YF1429200]
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000530387100002
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
EI Accession Number20201908616188
EI KeywordsCMOS integrated circuits ; Cryogenics ; MOS devices ; Nanotechnology ; Threshold voltage
EI Classification NumberCryogenics:644.4 ; Electricity: Basic Concepts and Phenomena:701.1 ; Semiconductor Devices and Integrated Circuits:714.2 ; Nanotechnology:761
WOS KeywordINVERSION LAYER MOBILITY ; SI NANOWIRE MOSFETS ; TRANSISTORS ; PERFORMANCE ; TRANSPORT
Original Document TypeArticle
Citation statistics
Cited Times:1[WOS]   [WOS Record]     [Related Records in WOS]
Document Type期刊论文
Identifierhttps://kms.shanghaitech.edu.cn/handle/2MSLDSTB/119070
Collection信息科学与技术学院_硕士生
信息科学与技术学院_PI研究组_寇煦丰组
信息科学与技术学院_本科生
Corresponding AuthorKou, Xufeng
Affiliation1.ShanghaiTech Univ, Sch Informat Sci & Technol, Shanghai 201210, Peoples R China
2.Shanghai Inst Microsyst & Informat Technol, Shanghai 20050, Peoples R China
3.Univ Chinese Acad Sci, Beijing 101408, Peoples R China
4.ShanghaiTech Univ, Sch Informat Sci & Technol, Shanghai 201210, Peoples R China
5.Shanghai IC Res & Dev Ctr, Shanghai 201210, Peoples R China
6.Huali Microelect Corp HLMC, Shanghai 201314, Peoples R China
7.Hong Kong Univ Sci & Technol, Dept Elect & Comp Engn, Hong Kong, Peoples R China
First Author AffilicationSchool of Information Science and Technology
Corresponding Author AffilicationSchool of Information Science and Technology
First Signature AffilicationSchool of Information Science and Technology
Recommended Citation
GB/T 7714
Wang, Zewei,Tang, Zhidong,Guo, Ao,et al. Temperature-Driven Gate Geometry Effects in Nanoscale Cryogenic MOSFETs[J]. IEEE ELECTRON DEVICE LETTERS,2020,41(5):661-664.
APA Wang, Zewei.,Tang, Zhidong.,Guo, Ao.,Luo, Xin.,Cao, Chengwei.,...&Kou, Xufeng.(2020).Temperature-Driven Gate Geometry Effects in Nanoscale Cryogenic MOSFETs.IEEE ELECTRON DEVICE LETTERS,41(5),661-664.
MLA Wang, Zewei,et al."Temperature-Driven Gate Geometry Effects in Nanoscale Cryogenic MOSFETs".IEEE ELECTRON DEVICE LETTERS 41.5(2020):661-664.
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